1. Field of the Invention
The present invention relates to an apparatus for driving a display apparatus such as an active matrix type liquid crystal display apparatus.
2. Description of the Background Art a typical prior art system is shown in FIG. 29. On a display panel 11 which forms an active matrix liquid crystal display apparatus, source lines 01 to 0N and gate lines L1 to LM are formed in a matrix. A thin film transistor T is arranged at each of the intersections of the source lines and gate lines. Through the transistors T, voltages of the source lines 01 to 0N are selectively supplied to pixel electrodes P. The source lines 01 to 0N are connected to a source driver 12 which is composed of a semiconductor integrated circuit. The source driver 12 selects one voltage from among eight different voltages V0 to V7 in total of a reference voltage source 13 in accordance with display data D0 to D2 each consisting of three bits and each corresponding to each source line 0k (k=1 to N). It then supplies selected voltages to the source lines 01 to 0N. A gate driver 14 composed of a semiconductor integrated circuit outputs gate signals G1 to GM to the gate lines L1 to LM. During one horizontal scanning period when each gate signal Gj (j=1 to M) is being supplied, the source driver 12 supplies voltages corresponding to the gradations of then respective pixel electrodes P, to the source line 0k.
FIG. 30 is a block diagram concretely showing a partial constitution of a prior art source driver 12 as shown in FIG. 29. The source driver 12 comprises decoder circuits FRk (k=1 to N) which individually correspond to the respective source lines 01 to 0N, respond to each data d0 to d2 corresponding to gradation display data D0 to D2, and selectively supply the eight different voltages V0 to V7 from the reference voltage source 13 to the source lines 0k through analog switches ASW0 to ASW7 to which signals S0 to S7 are respectively supplied, whereby eight-level gradation display is realized.
In the prior art as shown in FIGS. 29 and 30, the voltages V0 to V7 corresponding to gradation levels are each supplied from the reference voltage source 13 to the source driver 12. Hence, input terminals of necessary number for receiving the voltages V0 to V7 are required, and additionally the analog switches ASW0 to ASW7 are needed which respectively correspond to the gradation levels. Accordingly, a reduction of the number of input terminals is desired. Furthermore, in order to realize cost reduction, it is desired to reduce the number of the analog switches ASW0 to ASW7 to reduce the chip size of the source driver 12 composed of a semiconductor integrated circuit.
The analog switches ASW0 to ASW7 of the source driver 12 each need to have a sufficiently low ON-state resistance in order to correctly write the level of a selected one of the voltages V0 to V7 in the source lines 01 to 0N of the display panel 11 which are connected outside the source driver 12. For this reason, the area the analog switches ASW0 to ASW7 occupy in the semiconductor ship is generally about ten times to several ten times as large as a logic circuit element which is turned on and off for computation within the source driver 12. Thus, the analog switches ASW0 to ASW7 account for a large area within the semiconductor chip of the source driver 12. Hence, an increase in the number of the analog switches ASW0 to ASW7 for higher levels of gradation display directly increase the chip size of the semiconductor chip.
According to the prior art as shown in FIGS. 29 and 30, for example, in the case of a 16-level gradation display using 4-bit display data, input terminals for sixteen different reference voltages are necessary, and additionally sixteen analog switches in total are necessary which correspond to the respective reference voltages.
Another prior art system in which a small-sized semiconductor is realized by reducing numbers of the input terminals for the reference voltages and the analog switches is disclosed in Japanese Unexamined patent Publication No. 6-27900, which was proposed by the inventor of the present invention. A basic constitution according to the latter prior art is similar to the art shown in FIG. 29, and a partial constitution of the source driver 12 is shown in FIG. 31. According to the latter conventional technique, four different reference voltages V0, V2, V5 and V7 in total are generated in the reference voltage source 13 and are supplied to a source diver 12a. In the source driver 12a, four analog switches ASW0, ASW2, ASW5 and ASW7 corresponding to the reference voltages V0, V2, V5, V7, respectively, feed the reference voltages V0, V2, V5 and V7 directly to source lines 0h (h=1 to N). In addition, voltages V1, V3, V4 and V6 are generated from vibration between these reference voltages, so that in total eight different voltages V0, V1, V2, V3, V4, V5, V6 and V7 corresponding to eight gradations are outputted. Hence, responding to data d0 to d2 which correspond to data D0 to D2 of eight-level gradation display, a decoder circuit GRh outputs a selected one of the reference voltages V0, V2, V5 and V7 to the source line 0h. Additionally the intermediate voltages V1, V3, V4 and V6 are outputted to source line 0h by time-sharing the reference voltages V0, V2, V5 and V7. For example, the intermediate voltage V1 is outputted by time-sharing the reference voltages V0 and V2 and alternately outputting the time-shared voltages to the source line 0h. If the reference voltage V7 is set to be higher than the reference voltage V0, the relationship between the voltages is V0&lt;V1&lt;V2&lt;V3&lt;V4&lt;V5&lt;V6&lt;V7. the analog switches ASW0, ASW2, ASW5 and ASW7 are on-off-controlled by signals AS0, AS2, AS5 and AS7, respectively.
For example, in the case where the intermediate voltage V3 between the reference voltages V2 and V5 is generated and applied to the source line 0h, in one predetermined outputting period, the decoder circuit GRh alternately turns on and off the analog switches ASW2 and ASW5 as shown in FIG. 32A, and generates a vibration voltage as shown in FIG. 32A. Thereby, due to the resistance and capacity of the source line 0h, the voltage of the source line 0h becomes similar to a voltage which is filtered by a low pass filter as shown in FIG. 32B and eventually becomes the averaged voltage V3 shown in FIG. 32C, which will be applied to the pixel electrodes P through the transistors T.
Once being applied to the pixel electrodes P, voltages are held by a capacity between the pixel electrodes P and a common electrode disposed facing the pixel electrodes P through the liquid crystal. This operation is repeated for every one of the gate lines L1 to LM with respect to the source lines 01 to 0N, whereby the voltages V0 to V7 are held over one vertical period, for example.
The prior art of FIGS. 31 and 32 only needs in total four different reference voltages V0, V2, V5 and V7 for gradation display using the eight-level gradation display data D0 to D2 each composed of three bits. Consequently only the four analog switches ASW0, ASW2, ASW5 and ASW7 in total are necessary. Thus, the eight different voltages V0 to V7 corresponding to the respective gradations can be used by the reference voltages and analog switches whose numbers do not exceed the number of gradations. Accordingly, as compared with the prior art as shown in FIGS. 29 and 30, the number of the reference voltages which are generated by the reference voltage source 13 is smaller, and correspondingly the number of the analog switches can be reduced. Hence, the semiconductor ship of the source driver 12 can be small-sized, which in turn suppresses a consumption current. This eventually realizes lowered cost and high density packaging.
However, in practice, particularly in liquid crystal display apparatuses for office automation equipment, in order to obtain a further small-sized semiconductor ship, further higher levels of gradation display semiconductor chip, further higher levels of gradation display and further reduction of input terminals in number are demanded.